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Life & Diary

2024

连续两天的深夜奋斗

一个魔幻的周末

Paper Reading

sim

ISPASS'14 Simulating DRAM controllers for future arch

papers

Roofline model

Computer Architecture

books

Modern processor design

Review of SuperScalar Organization

Review of SuperScalar Technology

Other: CDC 6600 Scoreboard

Computer Architecture:A Quantitative Approach

Data-Level Parallelism

Thread-Level Parallelism

other: Pipeline time diagrams and bottleneck analysis

arm

snippets

memory model and branch instruction

risc-v

sbi & opensbi

snippets

memory order

single core memory order

OS Development and Usage

linux usage

resolving linking issues

the C Pre-Processor(CPP) usage

the C runtime

about abi

System-V abi

git

os 2024 nju

操作系统状态机

linux kernel

build process

kernel build process

kernel init -- asm

Language learning

python

metaclass and class defination in python

Python function parameter parsing

Static and Runtime Name Resolution

python import statement

fluent_python reading note

regular expression in python

cpp

beginning c++20

ch2 basic type

ch3 Dealing with basic data types

ch4 Control Flow

ch5 Arrays and Loops

ch6 Pointers & References

ch7 string

ch8 function

ch9 vocabulary types

ch11 module

ch12 define a class

ch13 operator overloading

ch14 inheritance

ch15 polymorphism

ch16 exception

ch17 template

ch19 first-class function

现代c++语言核心特性解析

右值引用

constexpr常量表达式

c++新经典

迭代器

Simulators

Debuging gem5 & Debuger usage

pdb handbook

gdb

ch4 debuging in gdb

ch5 debuging in gdb

ch9 debuging in gdb

ch10 debuging in gdb

ch17 debuging in gdb

Debugging Techniques

debug c/cpp macro

gem5 simulator

gem5 archtecture

gem5 build process analysis

gem5 simobject source code analysis

gem5 startup process

gem5 event driven programming

ISA independence in gem5

SimObject creation in gem5

gem5 debug tips

first instruction run in SE mode

gem5 cpu model

_m5 in gem5

ThreadContext vs ExecContext

Probe system in gem5 (Simpoint example)

Weak simpoint support in gem5

Out Of Order cpu model in gem5

gem5 RISC-V ISA implement

qemu

qemu build process

open xiangshan

xiangshan simulation environment

xiangshan fs workload gen

xiangshan gem5

xiangshan gem5 arch

xiangshan fetch

xiangshan iew

xiangshan unaligned load

Additions to the commit phase(squash, trap ...)

Load Store Unit

o3 memrequest

source code of gem5

base

extensible.hh

request & packet

callback.hh

debug.hh

mem

port.hh

backdoor.hh

abstract_mem.hh

physical.hh

configs

overview of all config files

cpu

pred

tage_base

minor

buffer.hh

dyn_inst.hh

pipeline.hh

o3

rename.hh & rename.cc

rob.hh & rob.cc

iew.hh & iew.cc

commit.hh & commit.cc

fu_pool & fu

InstructionQueue

DependencyGraph

load store queue

load store queue unit

pc_event

reg_class.hh

timebuf.hh

activity.hh

sim

System.hh

process.hh

fd_entry & fd_array

arch

generic

pcstate.hh

decoder & decoder cache

Compiler

tvm

vta

vta for developer

dragon book

Lexical Analysis Handout

Syntax Analysis Handout

Syntax-Direted Translation Handout

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Modern processor design

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gdb

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gem5 simobject source code analysis ​

gem5 simobject source code analysis